The pseudorandom test pattern generation for bist 基于內(nèi)建自測試的偽隨機測試向量生成方法
Automatic test pattern generation for multi - clock digital system based on s amp; amp; cct 基于安全充分捕獲技術的多時鐘數(shù)字系統(tǒng)測試矢量生成
An automatic test pattern generation ( atpg ) algorithm for deliberately selected delay faults is presented to cope with the crosstalk - induced delay effects on longer paths 由于電路中較長的通路具有較短的松弛時間,因此容易因為串擾問題產(chǎn)生時延故障。
In this way , a simple and direct relation was build up between logical transitions and dynamic current , which makes possible iddt testing pattern generation on logical level 該方法在電路邏輯跳變與電路動態(tài)電流之間建立了一種簡單直觀的關系,使得動態(tài)電流測試產(chǎn)生能夠在邏輯級上得以實現(xiàn)。
Based on the analysis and research on fan algorithm , an iddt test pattern generation algorithm for stuck - open faults is present . in the case of ignoring hazards , for the stuck - open faults in cmos circuits , the feasibility of transient current test generation based on fan algorithm is discussed 本文采用啟發(fā)式搜索的方法,基于對fan算法的分析,在不考慮冒險的情況下對于cmos電路中的開路故障,探討了利用fan算法進行瞬態(tài)電流測試生成的可能性。